Yoonjin Kim

Ph.D. Student, Department of Computer Science

Texas A&M University, College Station, TX 77843-3112

Yoonjin Kim

Contact me

Office : 514C H.R.Bright Building

Home : 1501 Harvey Road Apt. #549, College Station, TX 77840

Phone : 979-847-8574

Cellular Phone : 979-422-3896

E-mail : ykim@cs.tamu.edu

Homepage : http://students.cs.tamu.edu/ykim

Education

[1] 03/1995~02/2003

Degree : B.S. Information and Communication Engineering

University : Sungkyunkwan University, South Korea

Laboratory : VLSI Algorithmic Design Automation Laboratory

Advisor : Prof. Jundong Cho

[2] 03/2003~02/2005

Degree : M.S. Electrical Engineering and Computer Science

University : Seoul National University, South Korea

Thesis title : Domain-Specific Optimization of Coarse-Grained Reconfigurable Architecture

Laboratory : Design Automation Laboratory

Advisor : Prof. Kiyoung Choi

[3] 08/2006~ Current

Degree : Ph.D. Computer Engineering

University : Texas A&M University, College Station, USA

Dissertation title :

Laboratory : Embedded Systems & Codesign Group

Advisor : Prof. Rabi N. Mahapatra

Research Interests

System-on-Chip, Embedded Systems

VLSI CAD & Design Automation

Hardware/Software Co-design

Embedded Processor Architecture,

Coarse-Grained Reconfigurable Architecture

Experience

[1] 07/1998 ~ 01/2001 - Military Service

Affiliation : Maintenance Squadron, Field Warfare Maintenance Station,

Suwon Base of Combat Aircraft, ROKAF(Republic of Korea Airforce)

Mission : Maintenance of electrical and electronic Systems of combat aircraft

Discharge : an Airman First Class of ROKAF

[2] 03/2003 ~ 06/2003 - Teaching Assistant

Affiliation : School of EE/CS, Seoul National University

Course : Digital System Design(undergraduate course)

Professor : Kiyoung Choi

[3] 03/2003 ~ 02/2005 - Research Assistant

Affiliation : School of EE/CS, Seoul National University

Work : Reconfigurable Processor Design

Professor : Kiyoung Choi

[4] 03/2005 ~ 07/2006 - Research Staff

Affiliation : Inter-University Semiconductor Research Center in Seoul National University

Work :

[1] Chip implementation of coarse-grained reconfigurable architecture

[2] Implementation of design space exploration flow and mapping tool

for reconfigurable architecture

[5] 09/2006 ~ current - Research Assistant

Affiliation :Dept. of Computer Science, Texas A&M University

Work :

[1] COTS Microprocessor Evaluation for Avionic Systems

[2] Reconfigurable Computing for High Performance & Low Power Embedded Systems

Professor : Rabi N. Mahapatra

Course-work

Undergraduate Courses (Sungkyunkwan University)

[1] Material, Semiconductor

Physics in Electronics, Semiconductor Electronics,

Properties of Electronic Materials

[2] Analog Circuits

Electronic Circuits 1, Electronic Circuits 2

[3] Digital Circuits

Digital Logic, Digital Systems, VLSI Design Automation,

Computer Architecture, Integrated Circuits

[4] Communication Systems

Communication System, Digital Communications

[5] Signal Processing

Signals and Systems, Digital Signal Processing,

Probability and Random Process

[6] Computer Network

Data Communications, Computer Network,

Java Network Programming

[7] Programming Language

Fortran language, Java laguage,

C language, Matlab1, Matlab2

Graduate Courses (Seoul National University)

[1] VLSI/SoC CAD

System-On-Chip Design Automation,

Introduction to Computer-Aided Design

[2] Computer Architecture

Topics in Computer and VLSI : On-chip Communication Network,

Computer Organization and Design

[3] Compiler & Operating System

Advanced Compiler

Topics in Operating System

[4] HW/SW Co-Design

Co-design Methodology for System Design

Graduate Courses (Texas A&M Univeristy)

[1] Algogrithm

Analysis of Algorithms

[2] Computer Architecture

Computer Architecture

Special Topics in Chip Multi-Processor Architecture

[3] Writing

Writing for Publication

[4] Seminar

Graduate Seminar of Computer Science/Computer Engineering

Research Project

[1] 05/2003~01/2004 - Development of Pathway Viewer

Website : http://rospath.ewha.ac.kr/toolbox/PathwayViewerFrm.jsp

Sponsor : Interface Infotech Co. (IMT-2000)

Director : Kiyoung Choi

Introduction :

The project goal is development of ROSPath (Reactive Oxygen Species

Pathway) Viewer that shows this two level pathway graphically.

Assigned work :

[1] Development of GUI interface of ROSPath Viewer

[2] Graph drawing algorithm implementation

[2] 10/2003~03/2004 - Development of Reconfigurable Hardware

Website : http://poppy.snu.ac.kr/project_home/itsoc/itsoc.htm

Sponsor : Ministry of Knowledge Economy

Director : Kiyoung Choi

Introduction :

The project goal is development of coarse-grained reconfigurable hardware for multimedia applications.

Assigned work :

[1] Multimedia application benchmark

[2] 2-Dimension reconfigurable ALU array specification

[3] RT-level design of reconfigurable ALU array and verification on FPGA

[4] H.263 encoder evaluation on reconfigurable SoC platform

[3] 09/2004~ 07/2006 - MPEG-4 Decoder and 3D Graphics Accelerator

Design Based on Reconfigurable Structures

Website : http://poppy.snu.ac.kr/project_home/kosef_reconf/kosef_reconf.htm

Sponsor : Korea Science & Engineering Foundation

Director : Kiyoung Choi

Introduction :

In this project, we develop a reconfigurable processing element array and

implement kernels of MPEG-4 decoder and 3D accelerator on it.

Assigned Work :

[1] SystemC modeling of reconfigurable architecture

[2] H.264 encoder/decoder analysis

[3] GUI based mapping tool development

[4] Mapping the functions of H.264 onto reconfigurable array

[5] RT-level reconfigurable architecture optimization for H.264 and 3D Graphics

applications

[6] RTL model verification on FPGA

[7] Chip implementation of reconfigurable architecture

[4] 04/2006~ 07/2006 - Development of Reconfigurable Array Core for Mobile

Multimedia Applications

Website : http://poppy.snu.ac.kr/english/research/projects.php

Sponsor : Ministry of Knowledge Economy

Director : Kiyoung Choi

Introduction :

In this project, we develop power-conscious reconfigurable processing element array,

automatic code generation tool(compiler) and simulator for H.264 decoder, 3D-graphics

and MPEG-4/ AAC decoder

Assigned Work :

[1] H.264/MPEG-4 AAC decoder and 3D graphics code optimization

[2] Low power reconfigurable array structure implementation

[3] Development of code mapping algorithm

[4] Development of SoC platform including reconfigurable array

[5] Chip implementation of power-conscious reconfigurable architecture

[5] 01/2007~ - Evaluation and Guidelines to COTS Microprocessors in Avionics

for Safety-Critical and Real-Time Applications

Website :

Sponsor : Federal Aviation Administration , United States Department of Transportation

Director : Rabi N. Mahapatra

Introduction :

The intent of this project is to provide findings about saftey issues in using today's microprocessors on aircraft.

The project is being performed in multiple phases with participation from avionic system developers (BAE Systems,

The Boeing Company, Lockheed Martin and Smith Aerospace) and Federal Aviation Administration organizations

responsible for aircraft safety research and development.

Phase 1 established the project scope and identified the research parameters. Current trends toward using COTS

microprocessors presents safety challenges, especially with growing design complexity, the vast array of supported

features and limited design documentation. A formal framework for the approval of COTS microprocessors in aerospace

systems is essential. This project proposes a Microprocessor Approval Framework that is applicable to COTS microprocessors.

Assigned Work :

[1]Performance estimation of freescale 8540 on Simics for safety-critical and real-time applications

[3] Performance comparision between Simics and real hardware.

Skills

Programming Language :

C/(Visual)C++, JAVA

EDA/CAD :

Language : VHDL, SystemC

Tools :

[1] IDE : Xilinx ISE, Altera Quatus, ADS

[2] Simulation : Modelsim, Seamless CVE, ConvergenSC, Simics

[3] Systhesis : SynplifyPro, Leonardo Spectrum, Design Compiler

[4] Place & Routing Tool : Astro, Apollo

Awards

[1] Yoonjin Kim, Ilhyun Park, Bronze Prize, Chip-Design Contest sponsored by Korean Intellectual Property Office, "Design of Coarse-Grained Reconfigurable Architecture for Mobile Multimedia Applications ," December 2006

[2] Ilhyun Park, Yoonjin Kim, Chulsoo Park, Jeongki Son, Manhwee Jo, Kiyoung Choi, Demo section Second Prize, SoC International SoC Design Conference 2006 Chip Design Contest, "Chip Implementation of a Coarse-Grained Reconfigurable Architecture," October 2006

[3] Yoonjin Kim, Chulsoo Park, Ilhyun Park, Prize for Excellence, 1st SoC Design Contest sponsored by Ministry of Commerce, Industry and Energy, South Korea, "Design of Coarse-Grained Reconfigurable Architecture," December 2005

[4] Yoonjin Kim, Mary Kiemb, Kiyoung Choi, "Efficient Design Space Exploration for Domain-Speciific Optimization of Coarse-Grained Reconfigurable Architecture," SoC Design Conference sponsored by The Institute of Electronics Engineers of KOREA[IEEK] May 2005, IEEE SSCS/EDS Seoul Chapter Paper Award

[5] Yoonjin Kim, Excellent Graduation Thesis Award given by Korea IT Industry Promotion Agency[KIPA], "Domain-Specific Optimization of Coarse-Grained Reconfigurable Architectures," IT-SoC(Best) 2005-01

Patents

[1] Yoonjin Kim, Ilhyun Park, Kiyoung Choi, Yunheung Paek, "Configuration Cache Capable Low Power Consumption and Coarse-Grained Reconfigurable Architecture including the Configuration Cache therein," Korea, Yoonjin Kim, 2007-03-20, 20070023922, 2008-07-07

[2] Yoonjin Kim, Mary Kiemb, Chulsoo Park, Jinyoung Jung, Kiyoung Choi, "Resource Sharing and Pipelining in Coarse-Grained Reconfigurable Architectures," Korea, Yoonjin Kim, 2005-02-07, 200511451, 2007-03-29.

[3] Jongeun Lee, Yoonjin Kim, Jinyong Jung, Shinwon Kang, Kiyoung Choi, "Coarse-Grained Reconfigurable Architecture for Supporting Conditional Execution," Korea, Jongeun Lee, 2005-01-31, 20058669, 2007-02-26.

Publications

[2009] Third year (Ph.D. student in Texas A&M University, College Station, Texas)

[1] Yoonjin Kim, and Rabi N. Mahapatra, "Paper title omitted for blind review," prepared for IEEE ACM Design Automation Conference, 2009

[2] Yoonjin Kim, and Rabi N. Mahapatra, "Paper title omitted for blind review," submitted to IEEE ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, February 2009

[2008] Second year (Ph.D. student in Texas A&M University, College Station, Texas)

[1] Yoonjin Kim, Rabi N. Mahapatra, and Kiyoung Choi, "Cost-Effective Design Approach for Coarse-Grained Reconfigurable Architecture," submitted to IEEE Transactions on Very Large Scale Integration Systems

[2] Yoonjin Kim, and Rabi N. Mahapatra, "A New Array Fabric for Coarse-Grained Reconfigurable Architecture," IEEE EuroMicro Conference on Digital System Design, September 2008 (Acceptance rate 27% - regular papers).

[3] Yoonjin Kim, and Rabi N. Mahapatra, "Dynamic Context Compression for Low Power Coarse-Grained Reconfigurable Architecture," IEEE Transactions on Very Large Scale Integration Systems under minor revision.

[4] Yoonjin Kim, and Rabi N. Mahapatra, "Reusable Context Pipelining for Low Power Coarse-Grained Reconfigurable Architecture," IEEE/ACM Reconfigurable Architecture Workshop, April 2008

[5] Ilhyun Park, Yoonjin Kim, , Manhee Jo, and Kiyoung Choi, "Chip Implementation of Power Conscious Configuration Cache for Coarse-Grained Reconfigurable Architecture," The 15th Korean Conference on Semiconductors, February 2008

[2007] First year (Ph.D. student in Texas A&M University, College Station, Texas)

[1] Yoonjin Kim, and Rabi N. Mahapatra, "Dynamically Compressible Context Architecture for Low Power Coarse-Grained Reconfigurable Array," IEEE International Conference on Computer Design, October 2007 (Acceptance rate 21% - regular papers).

[2] Yoonjin Kim, Rabi N. Mahapatra, Ilhyun Park, and Kiyoung Choi, "Low Power Reconfiguration Technique for Coarse-Grained Reconfigurable Architecture," IEEE Transactions on Very Large Scale Integration Systems, accepted as a regular paper.

[2006] Second year (Research Staff in Inter-Univeristy Semiconductor Research Center in Seoul National University, Seoul, South Korea)

[1] Ilhyun Park, Yoonjin Kim, Chulsoo Park, Jeoongki Son, Manhee Jo, and Kiyoung Choi, "Chip Implementation of a Coarse-Grained Reconfigurable Architecture," International SoC Design Conference, October 2006

[2] Jonghee W. Yoon, Yoonjin Kim, Minwook Ahn, Yunheung Paek, and Kiyoung Choi, "Temporal Mapping for Loop Pipelining on a MIMD style Coarse-Grained Reconfigurable Architecture," International SoC Design Conference, October 2006

[3] Yoonjin Kim, Ilhyun Park, Kiyoung Choi, and Yunheung Paek, "Power-Conscious Configuration Cache Structure and Code Mapping for Coarse-Grained Reconfigurable Architecture," IEEE/ACM International Symposium on Low Power Electronics and Design, October 2006 (Acceptance rate 26%)

[4] Minwook Ahn, Jonghee W. Yoon, and Yunheung Paek, Yoonjin Kim, Mary Kiemb, and Kiyoung Choi, "A Spatial Mapping Algorithm for Heterogeneous Coarse-Grained Reconfigurable Architectures," IEEE/ACM Design, Automation and Test in Europe, March 2006 (Acceptance rate 28%)

[2005] First year (Research Staff in Inter-Univeristy Semiconductor Research Center in Seoul National University, Seoul, South Korea)

[1] Chulsoo Park, Yoonjin Kim, and Kiyoung Choi, "Domain-Specific Optimization of Reconfigurable Array Architecture," US-Korea Conference on Science, Technology, & Entrepreneurship, August 2005

[2] Yoonjin Kim, Mary Kiemb, and Kiyoung Choi, "Efficient Design Space Exploration for Domain-Specific Optimization of Coarse-Grained Reconfigurable Architecture," SoC Design Conference sponsored by The Institute of Electronics Engineers of KOREA[IEEK], May 2005, IEEE SSCS/EDS Seoul Chapter Paper Award

[3] Yoonjin Kim, Mary Kiemb, Chulsoo Park, Jinyong Jung, and Kiyoung Choi, "Resource Sharing and Pipelining in Coarse-Grained Reconfigurable Architecture for Domain-Specific Optimization", IEEE/ACM Design, Automation and Test in Europe, March 2005 (Acceptance rate 21%)

[2004] Second year (M.S student in Seoul National University, Seoul, South Korea)

[1] Yoonjin Kim, Chulsoo Park, Shinwon Kang, Hyunjik Song, Jinyong Jung, and Kiyoung Choi, "Design and Evaluation of a Coarse-Grained Reconfigurable Architecture," International SoC Design Conference, October 2004

[2] Jongeun Lee, Yoonjin Kim, Jinyong Jung, Shinwon Kang, and Kiyoung Choi, "Reconfigurable ALU Array Architecture with Conditional Execution," International SoC Design Conference, October 2004

[3] Yoonjin Kim, Jongeun Lee, Jinyoung Junng, Shinwon Kang, and Kiyoung Choi, "Design of Coarse-Grained Reconfigurable Hardware," SoC Design Conference sponsored by The Institute of Electronics Engineers of KOREA[IEEK] April 2004